FV-SOL-5 Logic Errors
TLDR
Logic errors arise from mistakes in the program’s control flow or conditional statements. These errors usually occur when the code’s behavior deviates from its intended purpose, not because of a flaw in the underlying arithmetic but due to a conceptual mistake in implementing rules or boundaries
Code
Classifications
Boundary Misalignment (FV-SOL-5-C1)
Occurs when code fails to respect predefined boundaries or intervals (e.g., epochs, time windows, thresholds)
Incorrect Conditionals (FV-SOL-5-C2)
Results from incorrect conditions in if
statements, loops, or switches, causing unintended branching in code execution
e.g. a function meant to handle reward calculation might incorrectly check for block.number >= lastRewardBlock
instead of block.number > lastRewardBlock
, causing rewards to be skipped or duplicated
Improper State Transitions (FV-SOL-5-C3)
A contract that has a specific progression (e.g., setup, running, paused) may mistakenly allow state-changing functions to execute out of order, leading to potential exploitation
Misordered Calculations (FV-SOL-5-C4)
Errors from improper indexing or referencing in mappings, often due to incorrect key choices or updates
Event Misreporting (FV-SOL-5-C5)
Failing to emit an event during a critical update like reward distribution, making it hard to track transactions or actions on-chain
Mitigation Patterns
State Machine Design (FV-SOL-5-M1)
The State Machine Design mitigation pattern is a robust approach for managing complex workflows or processes with defined states
Fail-Safe Defaults (FV-SOL-5-M2)
Use safe defaults in case of unexpected conditions or edge cases
Unit Testing on Edge Cases (FV-SOL-5-M3)
Implement exhaustive tests for each function, focusing on boundary values, extreme inputs, and edge cases
Actual Occurrences
Content
https://www.linkedin.com/pulse/state-machine-design-pattern-insolidity-luis-soares-m-sc-/
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